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The pace of advancement of chip manufacturing process is slowing down. We believe that looking for this answer will probably start with the history of chip development. As early as the 1980s and 1990s, whether Intel, IBM or TMSC (TSMC) announced that their transistor products have exceeded The next nanometer level, or the wafer fab of its chip into micron-level echelons, is enough to be called a shocking event for the industry. For example, in 1985, Intel's 80386 processor used a 1 micron manufacturing process; at the end of 2004, micron size was completely abandoned, and the adoption of the 90-nm Winchester AMD64 and Prescott Pentium4 became a new standard for the industry at that time.
However, the process speed of silicon chips has been slowing down recently. The processors, sensors, and memory chips used in digital devices at this stage are basically based on 45nm or 60nm, because except for Intel, there is almost no silicon chip product or technology that can reach 32nm, let alone 22nm.
The bottleneck of the traditional manufacturing process is that the top-down, layer-by-layer manufacturing methods that are commonly used in the manufacturing process of the chips already have a technical bottleneck. Even with the latest atomic layer deposition technology, the chip process is further brought to 22 nm. , 16 or even 14nm, and the "three-dimensional" structure of silicon transistors, I am afraid there is no longer a way to go.
We know that the volume of an atom is very small. For example, a hydrogen atom is only about 0.1 nm, a germanium atom's volume is about 0.3 nm, and an atom on a silicon chip is about 0.2 nm. In this way, it can be correctly understood that a few hundred atoms can be clustered on a 22- or 16-nm silicon chip, but this is not the size of a certain transistor. It is actually an effective measure of the distance of discrete chip components. In the 22nm chip, this manufacturing process is currently only controlled by the Intel family, and its related chip product IvyBridge is also about to face the market. Among them, the high-K dielectric layer is only 0.5nm thick, equivalent to a thickness of 2 to 3 atoms. .
However, the problem is that there is no manufacturing technology in the world that is perfect. When we affect the entire chip because of an unsuitable atom, it will no longer be possible to create a reliable, cost-effective, high-quality circuit.
Breakthrough may be "supplemental technology."
So, how should we break the 14nm technical bottleneck? Perhaps the only choice is to change the manufacturing methods of existing chips. Now researchers spend a lot of time and money each year in the existing layer-by-layer etching technology, but this is not Solve the problem.
Responses over the next few years should focus on those temporary complementary technologies, such as IBM's "siliconglue" and Invensas' chip-stacking technology, which can reduce energy consumption, improve single-chip performance, and can aggregate more transistors. The key technology to the same wafer is to reduce gate leakage to control power consumption and build more components on a single wafer.
Fortunately, Intelâ€™s recently announced 14nm roadmap has already responded to our speculations about breaking the 14nm technology bottleneck. Intel's answer is graphite chips, photons or quantum computers, or the move to mobile computing. However, no matter what kind of technology is adopted, there is no need to worry too much. If the never-ending silicon chip manufacturing process teaches people anything, it is that computers in the future will certainly become faster, cheaper and more effective.
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